Hello All,I'm trying to correct some intermittent behaviour in my video application. I think I've got timing issues around my DRAM. I'm using a frame buffer to all different video frame rates for output and input, and I'm connecting it to a bank of DDR2 SDRAM on the top banks of a Cyclone III EP3C16C8N. I'm limited to 167MHz, but my bandwidth should not be a problem; the video is 15bits wide right now, but I'd like to push up to 24bpp. Q. What is the right way to connect the DDR2 to the Frame Buffer? 1. Through a bridge? 2. Directly? My understanding is that a bridge is useful for a) replacing concurrency with arbitration and hence reducing fabric use and fanout hence increasing fmax; but my system has two masters (fb.read, fb.write), and one slave so still quite simple (see image of sopc builder). Also, it seems (but I can't find it in writing) that the frame buffer would have the correct arbitration logic for just this situation. Also, by enabling the 'use separate clocks...' option in the frame buffer parameters it will handle clock crossing. Q. Hence can I conclude that the frame buffer is effectively a bridge and that putting a 'pipeline bridge' between the frame buffer and the ddr2 would be redundant? (A pipeline bridge was recommended by a local distributor's FAE) Q. Also, a half rate bridge would be a bad idea since I'd lose my ability to burst past two words to the DRAM? Am I right saying that a half rate bridge is more appropriate for a CPU instruction master or other device where latency, not bursting, is a priority? Q. If I chose 'half' rate on my 'DDR2 SDRAM High Performance Controller', am I essentially putting a half rate bridge in front of my controller? Will the controller still burst past two words? I'm confused!! All help will be greatly appreciated. Many Thanks, Brent.
You're not that confused. :)Q1: In your case, directly Q2: Yes, it will be redundant. It doesn't make much sense to say that the FB component is a bridge but otherwise your reasoning is correct: - In a SOPC with just 2 masters and 1 slave, there is nothing to gain by inserting a pipeline bridge. - Since the FB component can use different clocks for the -ST and the -MM interfaces, you don't need a dual clock bridge. Q3: Correct. Q4: Don't know, actually.
Thanks rbugalho,RE Q4, I've got a feeling that it's not after reading on the issue briefly... If anyone out there in altera land knows better I'd love to hear.