FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6669 Discussions

VIP Scaler Register Readback

Altera_Forum
Honored Contributor II
1,054 Views

Hi, 

 

I am using the Scaler from the VIP ip collection and would like to read back the width and height registers (register 2 and 3) I have written. It would seem, however, that these register are write only? I have poked around in the .vho that gets generated for RTL simulation and it would seem as if the only possible output on the readdata output port is all '0' or all '1'. The output does not seem to depend on the address input.  

 

On the other hand, I have been able to read back the width and height registers on the test pattern generator. In general , is there any indication which registers can be read back and which are write only for the other VIP cores?  

 

Regards, 

Niki
0 Kudos
2 Replies
Altera_Forum
Honored Contributor II
380 Views

Hello, 

 

According to Appendix A of the VIP User Guide, the scaler, clipper and deinterlacer have write-only registers. All avalon slave interfaces with a wait_request signals exhibit the behaviour that you are describing although the Clocked Video Input and Clocked Video Output may be an exception.
0 Kudos
Altera_Forum
Honored Contributor II
380 Views

Hi vgs, 

 

Thanks - I've been through the UG a couple of times, but I must have missed that somehow.  

 

Regards, 

Niki
0 Kudos
Reply