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Verification on application of FFT ip core

Honored Contributor II

I'm working on an application that involves using an FFT of an analog signal. I am using the Cyclone V starter kit. 


To clarify, the analog signal is fed into on-board ADC and generates a 12-bit output. I wire these up in the relevant on-board input terminals. 

My Verilog code should store these digital input values into registers and assign them as inputs to "fft_real_in[16:0]" used here as well as the other required inputs (like clk, reset, etc): https://www.altera.com/support/support-resources/design-examples/design-software/verilog/ver-fft-32k... 

The final output I want from the FFT core will be stored in "fft_real_out[16:0]" and I can use the data freely. 


Did I get the concept right?
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Honored Contributor II

12bits input to fft requires fft input to be 12 bits (not more).  

Your fft output is both real and imaginary and choose the width you need. you will need scaling if you use Altera's block floating point architecture. 

you will need define start/end of frame and valid signals