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Honored Contributor I

Verilog - Digital Design Help!!!

I am working on a de-serial Design IP module, and I have to collect information into a single register containing Header + Message + CRC. I am receiving serial data which will bean header of 8 bits and depending on my header bit there is a decoder which decides the length of each message and if CRC is enabled then then it might also follow by CRC bits(no lengths specified). I have to fix these variable (Header + Message + CRC) into a single register each will be of different lengths. So I am confused that how do I make a variable length register which can hold different lengths of (Header + Message + CRC).  

I do not want any padding bits as the messages of longer lengths are less and more messages are of shorter length which will just increase the memory size. 

I will later on add time stamp into this to make it unique. Please Help!!!!
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Honored Contributor I

Does it need to be stored as a wide register? Normally you just deserialize the packet into memory and parse the data out from there.