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Altera_Forum
Honored Contributor I
712 Views

Verilog basics - isolating a bit in a sum

Inside an always statement: 

 

c <= a + b; 

s <= c[7]; 

 

What if I wanted to do: 

s <= (a+b)[7]; 

 

It does not work as such (compiler error), but it'd be convenient in that I do not want to store the result in a register and waste a clock cycle. 

 

Is there a way to do something like this? 

 

Thanks.
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2 Replies
Altera_Forum
Honored Contributor I
24 Views

You can simply define s as a wire and use an assign statement

Altera_Forum
Honored Contributor I
24 Views

Huh that makes sense. 

 

Thanks!
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