Video Image Processing with dynamic image size

[Altera_Forum]

Hello 

 I am developing a system using Video Image Processing from Altera I need to convert a RGB 4:4:4 (24 bits) video to YCbCr 4:2:2 (20 bits) To do that, I am using the following components:  Clocked Video Input CSC (Color Space Converter) -> RGB to YCbCr Chroma Resampler -> 4:4:4 to 4:2:2 Clocked Video Output  The CSC is the only component that don't need the image size as parameter My problem is that the video source can be in both HD or SD so I would need to dinamically adjust the components Is there anyway to do this dynamic reconfiguration? Or will I need to instantiate two of each component and select which one to use based on the video input format?  Thank you! Thiago

[Altera_Forum]

--- Quote Start ---  Hello   I am developing a system using Video Image Processing from Altera I need to convert a RGB 4:4:4 (24 bits) video to YCbCr 4:2:2 (20 bits) To do that, I am using the following components:   Clocked Video Input CSC (Color Space Converter) -> RGB to YCbCr Chroma Resampler -> 4:4:4 to 4:2:2 Clocked Video Output   The CSC is the only component that don't need the image size as parameter My problem is that the video source can be in both HD or SD so I would need to dinamically adjust the components Is there anyway to do this dynamic reconfiguration? Or will I need to instantiate two of each component and select which one to use based on the video input format?   Thank you! Thiago  --- Quote End ---     As I understand from your description, you have two sources which have an effect of changing the image size. Some of the solutions can be: 1. Have two designs for two sources and configure FPGA with the relevant design on-the-fly based on the source that you have selected. 2. Keep the bigger design among the two and see if there is any way to slice the parameters and signals of the bigger design to yield the parameters/signals of the smaller one.

[Altera_Forum]

I am currently using the Video and Image processing suite version 8.0. 

 The only component that you need to reconfigure is the clocked video output. This can be done via the avalon interface. The clocked video input will automatically detect format changes and you can check the status via its avalon interface.  Take a look at the documentation for the clocked video output. It's pretty straightforward.  On another note. You might consider not using the clocked video input and output cores for what you are doing. The Color Space Converter is all you really need. I'd just find a way to interface to it without the other components. I'm guessing you could use the CSC core without the Video IP control packets. And of course converting from 4:4:4 to 4:2:2 is trivial.  The other cores are pretty bloated and don't really provide functionality you need.  Jake

[Altera_Forum]

--- Quote Start ---  I am currently using the Video and Image processing suite version 8.0.  The only component that you need to reconfigure is the clocked video output. This can be done via the avalon interface. The clocked video input will automatically detect format changes and you can check the status via its avalon interface.  Take a look at the documentation for the clocked video output. It's pretty straightforward.  On another note. You might consider not using the clocked video input and output cores for what you are doing. The Color Space Converter is all you really need. I'd just find a way to interface to it without the other components. I'm guessing you could use the CSC core without the Video IP control packets. And of course converting from 4:4:4 to 4:2:2 is trivial.  The other cores are pretty bloated and don't really provide functionality you need.  Jake  --- Quote End ---    Thank you Jake! I did as you suggested. Now I am only instanciating the Color Space Converter without the video input/output. I did a small module to convert from 4:4:4 to 4:2:2 which only discards samples. The Altera resampler has an option to filter the output because it says that only discarding samples can result in aliasing. I don't know if that would be necessary in my case though. The Color Space Conversion is different for HD and SD signals. As I don't think that there is a dynamic way to change the coefficients of the converter, I instanciated two modules, one for HD and the other for SD. I'll select which one to use based on my input signal.  Thiago

[Altera_Forum]

Thiago Hello, 

 just like you I need rgb 4:4:4 to ycbcr 4:2:2 conversion. after you convert the rgb to ycbcr with the CSC, can you be more specific about the reduction of samples , just like you, I thought taking one pixel CbYCr and 2'nd pixel just the Y.   kindly regards amos

[Altera_Forum]

Hello amos 

 You could do the resampling by discarding one chroma sample for each pixel. It should look like this: -- Input: -- Y1Cb1Cr1, Y2Cb2Cr2, Y3Cb3Cr3, Y4Cb4Cr4 -- Output: -- Y1Cb1, Y2Cr2, Y3Cb3, Y4Cr4  You just need to figure some way to synchronize the Cb or Cr order (you should use the sync signals for this) to ensure the resulting image is correct.  Hope this helps  Best regards, Thiago

[Altera_Forum]

help me in my project of edge detection from real time video.

[Altera_Forum]

--- Quote Start ---  I am currently using the Video and Image processing suite version 8.0. On another note. You might consider not using the clocked video input and output cores for what you are doing. The Color Space Converter is all you really need. i'd just find a way to interface to it without the other components. I'm guessing you could use the CSC core without the Video IP control packets. And of course converting from 4:4:4 to 4:2:2 is trivial. Jake  --- Quote End ---   Hello, Jake! Did You use Color Space Converter and Chroma Resampler without CVI and CVO in Your own practice? In my case the 422 YUV 20-bit stream is coming to Chroma Resampler + Color Space Converter not from outside FPGA ( in which case CVI is used in front of all ), but originates within FPGA. Same thing with output - the RGB 30-bit stream coming from Chroma Resampler + Color Space Converter is not directed to outside FPGA ( in which case CVO is used ) , but stays within FPGA for further processing.