Hi,I try to implement a hardware design which scales an incoming video signal. With the new resolution the signal should output on a display. My Plan is to do this with the help of the “Video and Image Processing (VIP) Suite”. In the following figure you can see the structure with all interfaces which are necessary to make the video signal available in the VIP. http://i41.tinypic.com/30uzv5e.png The Clocked Video Input and the Clocked Video Output are used in a Qsys system. In the following figure you can see the components. http://i43.tinypic.com/mkd7bs.png This project is at the point that video signal is available in the VIP and can be looped through (without the scaler) to the screen. The next step is to check the scaler megafunction with 1:1 scaling factor. The Problem: When I use the scaler the screen displays only the first line of the entire image. I suppose there is a frame buffer required but I am not sure. Maybe you can give me some hints! Best regards, occino
You could double this to two lines to be safe (and make sure the CVO is set to only start outputting when the FIFO is nearly full), but this shouldn't be necessary. You could also try changing to the Scaler II (I think you are suing the old scaler at the moment).
I noticed that about every third or fourth time I programmed the FPGA the systems works. It seems to be a issue with the sync.In the settings of the CVO there is a input field "Fifo level at which to start output" Can you advise a value for this field? (The Resolution of the screen is 1366x768)
I would suggest you set the value of "Fifo level at which to start output" to almost the complete size of the FIFO - like the FIFO size minus 1 to 5 or something like that. This should reduce the risk of the CVO being starved of data at a critical time.