What clock sources are allowed for an EMIF reference clock?

[KCMurphy]

I need to generate a 200MHz reference clock for an LPDDR3 EMIF.  If I don't have any convenient clock available, how can I generate it on chip?  There seems to be an issue with using a PLL output as the reference source of an EMIF. 

The Altera-ese that I get in the error description is not particularly helpful.  Does this signal have to come externally, or can I generate it somehow internally.

Arria 10 10AX022C3U19I2SG

Quartus Pro 21.3.0

EMIF 19.2

[AdzimZM_Intel]

Hi KCMurphy,

The EMIF IP need to be driven from a dedicated clock source.

It's cannot uses the internally generated clock to drive the logic.

Regards,

Adzim

[KCMurphy]

And that dedicated clock has to be in the same bank as the EMIF block?

[AdzimZM_Intel]

Hi KCMurphy,

"And that dedicated clock has to be in the same bank as the EMIF block?"

• Yes it's must in the same bank as EMIF block

Regards,

Adzim

[AdzimZM_Intel]

We do not receive any further response regarding to this topic. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.