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What clock sources are allowed for an EMIF reference clock?

KCMurphy
New Contributor II
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I need to generate a 200MHz reference clock for an LPDDR3 EMIF.  If I don't have any convenient clock available, how can I generate it on chip?  There seems to be an issue with using a PLL output as the reference source of an EMIF. 

 

The Altera-ese that I get in the error description is not particularly helpful.  Does this signal have to come externally, or can I generate it somehow internally.

 

Arria 10 10AX022C3U19I2SG

Quartus Pro 21.3.0

EMIF 19.2

 

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AdzimZM_Intel
Employee
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Hi KCMurphy,


The EMIF IP need to be driven from a dedicated clock source.

It's cannot uses the internally generated clock to drive the logic.


Regards,

Adzim


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KCMurphy
New Contributor II
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And that dedicated clock has to be in the same bank as the EMIF block?

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AdzimZM_Intel
Employee
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Hi KCMurphy,


"And that dedicated clock has to be in the same bank as the EMIF block?"

  • Yes it's must in the same bank as EMIF block


Regards,

Adzim


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AdzimZM_Intel
Employee
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