FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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What does this SOPC message mean?

Honored Contributor II



I get the following message in my SOPC system: 

Info: clock_crossing_0: Only assert byte enables corresponding to the data widths of {VidIn:control, Interlacer:itlcontrol, Clipper:control} 


What does this mean? I cannot find any help in Quartus (10.1sp1) on this. The reason I ask is that I seem to have an overlapping address between the Interlacer and one of my other, custom written, cores. I use a 16 bit data bus (non-Nios) master and as far as I understand all VIP cores (except Scaler II) use native addressing. My custom core also has a 16-bit data bus slave control interface, but does not use native addressing (since it is depricated). The Interlacer sits at 0x1400 and my custom core at 0x1000. They both sit behind a clock crossing bridge which starts at 0x8000. Thus, seen from my master, the Interlacer is located at 0x9400 and the custom core at 0x9000. Writing to the Interlacer, however, messes up the custom core registers. 


I am under the impression that even though the DeInterlacer has only an 8-bit wide slave interface, its three registers will be located at 0x9400, 0x9402 and 0x9404 due to the native addressing mode.  



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