FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5990 Discussions

error in compiling the RapidIO IP for Stratix II GX: EP2SGX90FF1508C3.

Altera_Forum
Honored Contributor II
825 Views

Hi, 

 

I generated the rapidio IP from the MegaWizard Plug-in Manager for the device Stratix II GX: EP2SGX90FF1508C3. 

It generated the codes corresponding to the parameter specified in the MegaWizard Plug-in Manager then I added all the 

codes generated to the quartus project. Then I compiled, during compilation the following error came 

 

Error: Can't place 730 pins with 3.3-V LVTTL I/O standard because Fitter has only 653 such free pins available for general purpose I/O placement 

Error: Can't place pins due to device constraints 

Error: Can't fit design in device 

Error: Quartus II Fitter was unsuccessful. 3 errors, 12 warnings 

Error: Peak virtual memory: 432 megabytes 

Error: Processing ended: Wed Mar 09 15:29:40 2011 

Error: Elapsed time: 00:00:29 

Error: Total CPU time (on all processors): 00:00:29 

Error: Quartus II Full Compilation was unsuccessful. 5 errors, 36 warnings 

 

I am new to Quartus software please help me in solving this error.......
0 Kudos
2 Replies
Altera_Forum
Honored Contributor II
84 Views

Your design is using to many input/output ports on the FPGA. Try to reduce them. 730 ports is a lot...

Altera_Forum
Honored Contributor II
84 Views

Hi, 

 

Thank you for your advice  

I regenerated the IP using MEGA WIZARD with the different parameter and recompiled the design successfully :)
Reply