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What is the polarity of DCLK signal in EPCS16 ?

Altera_Forum
Honored Contributor II
1,217 Views

I am using cyclone iii ep3c25 fpga in which I have designed an sopc system which has altera spi ip. I want to access EPCS16 flash using this SPI. For that, what polarity should i kept for the sclk signal of spi? From datasheet of EPCS16 I got that the phase of DCLK is 1. but i couldn't find the polarity of dclk.

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Altera_Forum
Honored Contributor II
92 Views

If you take a look at the timing diagrams in the datasheet you will see that EPCS devices set the DATA output on DCLK falling edge and latch ASDI input on DCLK rising edge.

Altera_Forum
Honored Contributor II
92 Views

Yeah, but that determines the phase of dclk, which is 1 according to datasheet. But how can we figure out the polarity of dclk? By default, dclk is 0 or 1?

Altera_Forum
Honored Contributor II
92 Views

I presume this is irrelevant.  

EPCS will sample the ASDI input and latch the first bit of the command code when it detects the first DCLK rising edge after nCS has gone low. 

Then, if DCLK is normally high, it needs to go low just before starting the command sequence; but this will have no effect, since the EPCS status machine is still inactive, until the next rising edge.
Altera_Forum
Honored Contributor II
92 Views

 

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I presume this is irrelevant. 

--- Quote End ---  

 

Yes, as you can clearly see from the EPCS datasheet in Quartus config handbook. EPCS16 is also functionally compatible to industry standard SPI flash devices, e.g. M25P16, in case of doubt refer to the respective datasheets.
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