i'm currently designing an SFPDP receiver for defence application. I'm USING altgx ip core for the same. When i'm receiving the data im getting continuous high signal for SYNC . And showing fluctuating values in pattern detect and error detect.
What is the standard control code for the SFPDP protocol??
As I understand it, you are inquiring about the control code for a specific protocol. Sorry as I do not have visibility into the SFPDP protocol specs. As a workaround, you might want to cross check with the protocol specs documentation. Sorry for the inconvenience. Please feel free to let me know should you have any FPGA or ALTGX IP specific inquiries. I will be more than happy to assist you on.
Please let me know if there is any concern. thank you.