FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
6673 Discussions

What's the difference between area sequencer optimization and performance in qdr II

Altera_Forum
Honored Contributor II
‎01-28-2016 08:37 AM
1,080 Views

What's the difference between area sequencer optimization and performance in qdr II IP. 

The same qsys project, when using Performance(Nios II-based Sequencer), the timing is good, but when using Area(RTL Sequencer), the timing is bad. 

 

What puzzles me is how sequencer affects project timing?
0 Kudos

Link Copied

0 Replies
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.