Which goes first Interrupt or MWr?

FPGA Intellectual Property

PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

Which goes first Interrupt or MWr?

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Hi,

I am working on a project with the Stratix V Hard IP PCI Express with MSI interrupts. I want to send a regular MWr packet followed by a interrupt (legacy or MSI). The question is if I write the MWr to the tx_st_data line and raise an interrupt, which will be sent first? The packet beign written is small, just 4 DWs.

Being the interrupts are TLPs as well, I would think the first one to reach the IP goes out first, but I do not know if there is any reordering going on or of the credits could stop one but not the other. Or should I wait some time. Is there some way to tell when a packet sent on the tx_st_data line has been already shipped and is no longer sitting in the buffer?

Thanks

-G

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