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Altera_Forum
Honored Contributor I
931 Views

Why address space bytes allocated by QSYS does not match the SPI IP core ?

Hello everyone: 

I have a question: Why QSYS automatically allocates address space bytes that do not match the number of internal register address space bytes defined by the SPI IP core? 

Specific use is as follows: 

I use SPI(3wire serial)IP in QSYS (Quartus II 11.1sp2) ,Parameter settings see Figure 1, after the completion of the set up, use "Assign Base Addresses " function,but the number of bytes that QSYS automatically allocates is only 8 bytes(see Figure 2), it not match the register map of SPI IP core define.(see Figure 3). 

In addition,when the data width of the master port (Avalon MM) is 8 bits, no matter how the SPI sets the data bit width, the number of bytes that QSYS automatically allocates is 8 bytes.When the data width of the master port (Avalon MM) is 16 bits, no matter how the SPI sets the data bit width, the number of bytes that QSYS automatically allocates is 16 bytes,and so on. 

My question is : 

When the number of bytes that QSYS automatically allocates is 8 bytes,Which byte is the specific address of the "rxdata ",''txdata","status","control" and "slaveselect" register? 

Looking forward to your answer, thank you very much!
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5 Replies
Altera_Forum
Honored Contributor I
52 Views

Which version of QSys are you using? Which master is the SPI component connected to? Could you share your qsys file? 

I've tried on one of my designs and QSys does allocate 32 bytes, as expected. Of course in that case it doesn't allow the address 0x4f0, as it makes the decoding more difficult and suggests 0x4e0 or 0x500 instead.
Altera_Forum
Honored Contributor I
52 Views

Just to be sure, I tried with 8 and 16 bits wide Avalon masters and had the same results (32 bytes allocated). Did you try putting an Avalon MM Pipeline Bridge between your master and the SPI slave, to see if it changes anything?

Altera_Forum
Honored Contributor I
52 Views

I try putting an Avalon MM Pipeline Bridge between master port and the SPI IP , The parameter settings of Avalon MM Pipeline Bridge are as follows Figure 4. In the case,the number of SPI IP bytes that Qsys automatically allocates is 32 bytes(see Figure 5).  

 

 

At this time, the slave port of Avalon MM Pipeline Bridge connected to the master port of bus bridge module component(External_bus_to_Avalon.v) (see Figure 6), and the master port of Avalon MM Pipeline Bridge connected to all slave port of other components(see Figure 7) (The slave port of other components connected to the master port of bus bridge module component original). 

 

 

I want to confirm this method right. 

 

 

Looking forward to your answer, thank you!
Altera_Forum
Honored Contributor I
52 Views

it looks correct yes. Sorry for not replying earlier

Altera_Forum
Honored Contributor I
52 Views

It does not matter, thank you for your reply.

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