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Why does the auto precharge input signal disappear in Qsys for the DDR3 memory controller IP block when Hard Memory Interface is enabled?

The enable Auto-Precharge Control option remains selected, but if you change between not using the Hard interface to using it, the signal is no longer present in Qsys. This is targeting a Cyclone V SoC, IP is the DDR3 SDRAM Controller with UniPHY Intel PFGA IP.

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Hi JWils26,

 

Unfortunately hard memory controller doesn't support auto-precharge control and won't enable "local_autopch_req" as shown in attachment.

 

You can consider to use regular soft memory controller that support auto-precharge control (uncheck hard memory interface) option in DDR3 UNIPHY IP.

 

I am really sorry for any inconvenience cause.

 

Thanks

 

Regards,

NAli1

 

autoprecharge.png

 

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