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The emac_rx_reset is associated with the emac_rx_clk as one would expect, so why is the tx_reset not associated with the tx_clk? I traced it through the code and it is not clear why it would be like this.
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- Cyclone® V FPGAs
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Hello,
can you please share with me the piece of code that you have found?
thanks
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In the altera_hps_emac_interface_splitter_hw.tcl file:
#
# connection point emac_tx_reset
#
add_interface emac_tx_reset reset end
set_interface_property emac_tx_reset associatedClock emac_gtx_clk
set_interface_property emac_tx_reset synchronousEdges DEASSERT
set_interface_property emac_tx_reset ENABLED true
add_interface_port emac_tx_reset rst_tx_n_o reset_n Input 1
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Thank you very much for your sharing,
I will go through that with my internal team and reply to you ASAP.
Thanks
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