XXX. Sof was downloaded to FPGA, Contains a 5G LDPC IP,i find the signal (sink_ready) always low,

[晓孙0002]

I dowmload a xxx.sofwhich contains a 5G LDPC IP，I confirm the rst_n​ is high，but the 5G LDPC output signal (sink_ready)and (source_ready) is low,

I generated xxx.sof is not xxx_time_limited.sof.

[CheePin_C_Intel]

Hi,

As I understand it, you are observing an issue with 5G LDPC IP in hardware where the signaltap seems to be showing sink_ready stuck at 0. To facilitate further debugging, would you mind to try to perform Modelsim simulation with your design to see if you can observe similar issue. If similar issue is observed, you may also cross check with the simulation example generated by the 5G LDPC IP to see if can spot any anomaly. 

For your information, I have tested simulating the example design in Modelsim and seems like it is functioning.

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin

[晓孙0002]

LDPC IP in my hardware has been verified in Modelsim, and the simulation has been successfully compared with MATLAB. Only when it is verified in FPGA, it is found that the sink ready signal is low. When I added the input and output signals to HDL for verification, I connected them to the pin except for the sink [data]. I found that in post fit, the compiler automatically connected the signals to GND. I confirm that my reset signal is normal. The signals about LDPC are all 0

[CheePin_C_Intel]

Hi,

thanks for your update.

Would you mind to share with me a simple test design which could replicate your observation ie the signals connected to GND and also sink_ready stuck at low in hardware? I would like to look into it to see if can spot any anomaly.

Please feel free to let me know the specific device and devkit (if any) that you are using to replicate the observation?

Please share with me the specific steps that you are taking to replicate the observation or test the design. I would like to see if I can bring up a setup to replicate your observation.

Thank you.

[晓孙0002]

I used the Intel arria 10 GX official development board and wrote a new piece of code at home due to our illness. Attached is my engineering document.

I find that many internal signals of LDPC ﹣ 5g IP are optimized.

quartus prime pro 19.1​

[CheePin_C_Intel]

Hi, Thanks for your update. I have run compilation with your design in Q19.4Pro which was currently available in my local PC. As I checked the RTL viewer, post-mapping and post-fitting, I can see that the important signals ie data, clock, sink_sop/eop are still available. Just wonder if you are seeing the same as following: [cid:image001.jpg@01D5DE84.05929700] By the way, for testing purpose, just wonder if you have had a chance to create simple design with only 5G LDPC IP instance. Then feed dummy fix data and direct clock signal from oscillator. Just to check if after releasing reset, will the sink_ready go high. From the simulation and user guide, with clock and reset correctly, the sink_ready should be able to assert. Thank you. Best regards, Chee Pin