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Altera_Forum
Honored Contributor I
1,432 Views

a problems about using posedge

always @ (posedge clk or negedge alarm_in) 

begin 

if(cnt_s == set_s && cnt_m == set_m && cnt_h == set_h)  

alarm_outr <= 1'b1; 

else if(alarm_in == 1'b0) begin 

alarm_outr <= 1'b0; 

end 

Error (10200): Verilog HDL Conditional Statement error at timeinterrupt.v(43): cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct 

 

 

but if i change" posedge clk or negedge alarm_in" into "clk or alarm_in" 

it will be ok  

but it will warrning &#65292;Warning (10235): Verilog HDL Always Construct warning at timeinterrupt.v(103): variable "cnt_h" is read inside the Always Construct but isn't in the Always Construct's Event Control 

 

how to handle this problem?
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6 Replies
Altera_Forum
Honored Contributor I
89 Views

It is not possible to synchronize on both positive and negative edge of a clock. Evene worse if you want to trigger on two clocks. 

 

I suggest to synchronize everything on one clock. 

Then start with a check on the condition being zero for the remaining signal.
Altera_Forum
Honored Contributor I
89 Views

if i have two signal to determine the outcome, i can't put the outcome variable into two always blocks.... so i have to put them into one always block 

 

for : 

always @ ( in1 or in2) 

if (in1=1) a =b ; 

else .... 

 

i can't change them into  

 

always @ (in1) 

if (...) a=b ; 

 

always @ (in2) 

if(...) a =d 

 

so there is always some time i have to put some clock in one block; 

if i put them into one block,then i meet the problem like the previous one  

do u have good way to design or handle this situation?  

 

 

i try this way: 

alarm = ((cnt_s == set_s) && (cnt_m == set_m) && (cnt_h == set_h))? 1'b1:alarm_in; 

 

the same logic  

however it still warning this: 

Warning (10236): Verilog HDL Implicit Net warning at timeinterrupt.v(116): created implicit net for "alarm" 

 

 

:confused::confused::confused:
Altera_Forum
Honored Contributor I
89 Views

I think that your idea of : 

for : 

always @ ( in1 or in2) 

if (in1=1) a =b ; 

else .... 

 

works if you put only the signals in the sensitivity list of the always block.  

This generates a combinatorial function not triggered on any clock. 

 

Further, the lasty line of code that you propose: 

alarm = ((cnt_s == set_s) && (cnt_m == set_m) && (cnt_h == set_h))? 1'b1:alarm_in; 

 

is also good.  

The warning that you get is because you did not define a wire for the signal alarm. 

Add the wire declaration and it should be fine. 

 

 

 

 

--- Quote Start ---  

if i have two signal to determine the outcome, i can't put the outcome variable into two always blocks.... so i have to put them into one always block 

 

for : 

always @ ( in1 or in2) 

if (in1=1) a =b ; 

else .... 

 

i can't change them into  

 

always @ (in1) 

if (...) a=b ; 

 

always @ (in2) 

if(...) a =d 

 

so there is always some time i have to put some clock in one block; 

if i put them into one block,then i meet the problem like the previous one  

do u have good way to design or handle this situation?  

 

 

i try this way: 

alarm = ((cnt_s == set_s) && (cnt_m == set_m) && (cnt_h == set_h))? 1'b1:alarm_in; 

 

the same logic  

however it still warning this: 

Warning (10236): Verilog HDL Implicit Net warning at timeinterrupt.v(116): created implicit net for "alarm" 

 

 

:confused::confused::confused: 

--- Quote End ---  

Altera_Forum
Honored Contributor I
89 Views

Referring to your original code snippet 

always @ (posedge clk or negedge alarm_in) begin if(cnt_s == set_s && cnt_m == set_m && cnt_h == set_h) alarm_outr <= 1'b1; else if(alarm_in == 1'b0) begin alarm_outr <= 1'b0; end 

It does not involve dual clock edges as supected by nplttr, because alarm_in isn't a clock. The code uses the Verilog syntax for an asynchronous reset, but with a wrong order (and unpaired begin end). This way it should synthesisze correctly. If you think the order of the original code is essential, then you have a problem... 

always @ (posedge clk or negedge alarm_in) begin if(alarm_in == 1'b0) alarm_outr <= 1'b0; else if(cnt_s == set_s && cnt_m == set_m && cnt_h == set_h) alarm_outr <= 1'b1; end 

 

Generally, you should consider that an edge sensitive always block stands for a DFF, possibly with additional asynchronous inputs. It can be driven by only one clock. So one register can't appear in multiple always block as assignment target.
Altera_Forum
Honored Contributor I
89 Views

thanks i tried your way to design .... it can synthesized ... thanks again

Altera_Forum
Honored Contributor I
89 Views

thanks very much ...you give me another ideal to design ...

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