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Altera_Forum
Honored Contributor I
1,022 Views

about Merlin Burst Adapter

Hello, 

Now I'm writing an interface between Avalon bus and a LSI, changing Avalon bus signals(read, write,ect) to LSI control signals. An interface can deal with burst transfer is preferred. 

 

In Qsys Interconnect, I found this: The Qsys interconnect uses the Qsys Merlin Burst Adapter to accommodate the burst capabilities of each interface in the system, including interfaces that do not support burst transfers. 

 

Does it mean: when I adding the interface(burst transfer isn't supported) in Qsys, the Qsys can translate burst transfers into individual salve transfers automatically? 

 

Best regards, 

feng
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4 Replies
Altera_Forum
Honored Contributor I
72 Views

 

--- Quote Start ---  

 

Now I'm writing an interface between Avalon bus and a LSI, changing Avalon bus signals(read, write,ect) to LSI control signals. An interface can deal with burst transfer is preferred. 

 

--- Quote End ---  

 

 

Are you sure you need burst? Does the LSI interface use a start address followed by multiple data phases like a DDR, or can it just accept data on every cycle? If the latter is the case, then the Avalon components can post writes and prefetch reads on every clock cycle, so a burst interface is not required. 

 

Can you post a part number for the LSI device. I'll take a look. 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
72 Views

Thanks for you answer, Dave. 

 

The LSI need many clock cycles to return readdata, and also need many cycles to complete a write transfer. 

 

If the interface doesn't support burst transfer, what'll happen when the Nios starting a burst transfer? The Merlin Burst Adapter will translate burst transfer into individual salve transfers? 

 

regards, 

feng
Altera_Forum
Honored Contributor I
72 Views

If your LSI (I've NFI what it is - but I assume some serial bus) needs a lot of clocks to perform an action, it may be better to perform the LSI transfer completely asynchronously and have the Avalon master (eg nios) either poll for completion or (if very very slow) take an interrupt. 

That way you don't completely stall the nios cpu while your slow LSI transfer takes place, and you'll have complete control of the number of words read/written from the LSI slave in one transfer. 

The nios cpu can only do burst transfers for cache line fill/write, but doesn't normally have that enabled because it isn't necessary for internal memory or SDRAM/DDR.
Altera_Forum
Honored Contributor I
72 Views

Thanks, dsl. 

 

I implemented the custom component between Avalon master and the LSI synchronously. Did you mean that if the custom component don't support burst transfer, then burst transfers shouldn't happen? 

 

regards, 

feng
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