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Altera_Forum
Honored Contributor I
1,378 Views

avalon MM burst read command and waitrequest

Hi all, 

 

I'm realizing a custom Avalon MM Slave, which should be able to operate in burst mode. Focusing on burst READ commands, I have a doubt about the possibility that a single master asks for multiple read transaction in a row (without waiting any time between them). My slave can manage only one burst transfer at a time, what should I do in the case of multiple requests? Should I use waitrequest? 

 

I can't show here my VHDL code for business reasons, but what if I use an internal status variable and make waitrequest=1 when status=BURSTING (i.e. the slave is managing a burst transfer)? Does this work or the master won't receive any data if waitrequest=1 all the transaction duration long? 

 

I hope I have explained enough clearly, 

Thanks in advance, 

Luca.
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4 Replies
Altera_Forum
Honored Contributor I
95 Views

 

--- Quote Start ---  

 

I'm realizing a custom Avalon MM Slave, which should be able to operate in burst mode. Focusing on burst READ commands, I have a doubt about the possibility that a single master asks for multiple read transaction in a row (without waiting any time between them). My slave can manage only one burst transfer at a time, what should I do in the case of multiple requests? Should I use waitrequest? 

 

--- Quote End ---  

 

Yes. 

 

 

--- Quote Start ---  

 

I can't show here my VHDL code for business reasons, but what if I use an internal status variable and make waitrequest=1 when status=BURSTING (i.e. the slave is managing a burst transfer)? Does this work or the master won't receive any data if waitrequest=1 all the transaction duration long? 

 

--- Quote End ---  

 

Your interface state machine can assert waitrequest at the end of the clock period where you accept the read transaction, and keep it asserted until the last data phase of readdatavalid assertion. 

 

I just posted a tutorial on using the Avalon-MM Master BFM which include VHDL source code. Take a look at it. There is a burst example in the Modelsim simulation. 

 

http://www.alteraforum.com/forum/showthread.php?t=48928 

 

Use the BFM to test your component. My test example does not generate lots of different Avalon-MM sequences, but the example will be enough to get you started. 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
95 Views

 

--- Quote Start ---  

Yes. 

 

 

Your interface state machine can assert waitrequest at the end of the clock period where you accept the read transaction, and keep it asserted until the last data phase of readdatavalid assertion. 

 

I just posted a tutorial on using the Avalon-MM Master BFM which include VHDL source code. Take a look at it. There is a burst example in the Modelsim simulation. 

 

http://www.alteraforum.com/forum/showthread.php?t=48928 

 

Use the BFM to test your component. My test example does not generate lots of different Avalon-MM sequences, but the example will be enough to get you started. 

 

Cheers, 

Dave 

--- Quote End ---  

 

 

Thank you!! 

It works! 

 

I'll look at your tutorial for sure. 

 

Thanks again :)
Altera_Forum
Honored Contributor I
95 Views

 

--- Quote Start ---  

 

It works! 

 

--- Quote End ---  

 

Excellent! 

 

 

--- Quote Start ---  

 

I'll look at your tutorial for sure. 

 

--- Quote End ---  

 

I am sure you will appreciate using the BFMs. It makes the development of the slave interface much easier. 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
95 Views

You're definitely right, I've already used BFMs to validate my custom avalon slaves, but I didn't find out that specific master component since it was me who was issuing burst commands (and waiting for them to be completed every time). 

 

I have just read your tutorials and they are really good! I have to make a confession: the first time I used BFMs I followed an other tutorial by you: http://www.alterawiki.com/wiki/using_the_usb-blaster_as_an_sopc/qsys_avalon-mm_master_tutorial!!! You can't imagine how much it helped me! 

 

Thanks for your job, you're making a better world for us FPGA newbies! :)
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