Hi,I have been trying to test a design using Avalon ST Stratix V PCIE Hard IP with a 125MHz reference clock. I tried building the BFM and it seemed to work, but when I siumulate it I get warnings that the reference clock must be 100MHz, although I put in the Qsys TB file that the clock should be 125MHz and in the Megawizard plugin as well. I left it simulating anyways and ignored the warning and neither the root port of the endpoint nor my BFM could enter POLLING.CONFIG. The warning seems to have come from an internal compiled block ......xcvr_tx_plls_inst.pll.pll.atx_pll.tx_pll.<protected>.<protected>.<protected>.UI# Warning: The frequency of the reference clock signal differs from the specified frequency (100 MHz). I then tried to make a workaround. I assumed that the BFM does not support 125MHz reference like the root port and end point do. I tried then tried to reconfigure the BFM for a 100MHz refclk and made a new refclock, aligned to the one produced by the BFM, but at 125MHz. This actually came up better, the endpoint made it to POLLING.CONFIG, but the root port was still stuck alternating between the DETECT and POLLING stages:# INFO: 69621 ns RP LTSSM State: DETECT.QUIET# INFO: 72901 ns RP LTSSM State: DETECT.ACTIVE# INFO: 73877 ns RP LTSSM State: POLLING.ACTIVE# INFO: 86741 ns RP LTSSM State: DETECT.QUIET# INFO: 90021 ns RP LTSSM State: DETECT.ACTIVE# INFO: 90997 ns RP LTSSM State: POLLING.ACTIVE Any ideas? Is the BFM really limited to 100MHz refclocks? Any ideas what could be checked? -G
Below are the changes needed to run the simulation at refclk 125MHz:1. Open the .qsys, select refclk 125 MHz in the Avalon-MM Stratix V HIP for PCIe. 2. Connect the clock output from the Clock Source to refclk input of PCIe core in Qsys. 3. Hit 'Generate testbench system' to generate the testbench, then re-run the simulation.