FPGA Intellectual Property

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FPGA Intellectual Property

Discussions

Microtronix non-Avalon multi-port memory controller

question of io timing constraints of (r)gmii of the triple speed ethernet mac

FFT v6.1 - sink_ready de-asserting by itself

Long word length support in DSP Builder 7.1

Microtronix HyperDrive Multi-port DDR2 Memory Controller IP

Differences between Atlantic and Avalon Streaming Protocols

Clock enable bug with FIR compiler v3.3.1 and v6.1

VGA 24 bit Avalon???

DDR interface that spans multiple sides of the device

DDR II SRAM (not SDRAM) interface to Stratix II

FFT - block floating point scaling (AN 404)

What USB Phy would bolt up to a CAST CUSB core?

PAL-to-NTSC Conversion IP

Does Altera support ZBT SRAM for Stratix II devices?

Does Altera have USB 2.0 host core?

Featured Content

Tone Mapping Operator IP Malfunctioning

Unable to simulate DDR3 controller

AGILEX 5E : GTS AXI IP PCI Express : What is the mapping of the PCIe Header on _tuser_hdr[255:0]

Re: ALTPLL dynamic phase shift: c0/c1 shift in opposite directions; c2 does not shift (Stratix IV)

Re: ALTPLL dynamic phase shift: c0/c1 shift in opposite directions; c2 does not shift (Stratix IV)