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can not understand the figure of High-Performance controller ?

Altera_Forum
Honored Contributor II
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http://www.alteraforum.com/forum/attachment.php?attachmentid=10313&stc=1  

 

 

I can not understand the figure in "Chapter 3: Using High-Performance DDR, DDR2, and DDR3 SDRAM with SOPC Builder" 

what is the signal which the red arrow point to?
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Altera_Forum
Honored Contributor II
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That's a glitch.. Probably caused by combinational logic after the last flip-flop in the data path to those signals. 

 

If the signal was being used by a clock somewhere it would be an issue. But as long as it's stable before the next rising edge it should be ok for the date path. it's fine.
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