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compile error in A10 PCIe hard IP

I am getting this error message when elaborating a PCIe hard IP core with Avalon MM interface (build as a Qsys block with Platform Designer)

Error(13224): Verilog HDL or VHDL error at altpcieav_dma_hprxm_rdwr.sv(1543): index -1 is out of range [63:0] for 'rxm_address_reg' 

 

The hierarchical structure looks like this:

module pcie_core_pcie_a10_hip_0_altera_pcie_a10_hip_181_7tjtnma (

. . .

);

. . .

parameter bar2_address_width_mux_hwtcl = 0;

. . .

localparam avmm_bar2_size_mask = bar2_address_width_mux_hwtcl;

 

. . .

altpcieav_256_app #(

. . .

.BAR2_SIZE_MASK (avmm_bar2_size_mask),

. . . )

 

module altpcieav_256_app (

. . .

);

 

. . .

parameter BAR2_SIZE_MASK = 1;

 

. . .

altpcieav_dma_hprxm #(

. . .

.BAR2_SIZE_MASK (BAR2_SIZE_MASK),

. . . )

 

module altpcieav_dma_hprxm (

. . .

);

. . .

 

parameter BAR2_SIZE_MASK = 20;

 

altpcieav_dma_hprxm_rdwr #(

. . .

.BAR2_SIZE_MASK(BAR2_SIZE_MASK)

. . . )

 

module altpcieav_dma_hprxm_rdwr (

. . .

);

 

. . .

parameter HPRXM_BAR_TYPE = 64;

. . .

parameter BAR2_SIZE_MASK = 20;

. . .

 

assign HPRxmAddress_o = { {(HPRXM_BAR_TYPE-BAR2_SIZE_MASK ){1'b0}}, rxm_address_reg[BAR2_SIZE_MASK -1:0] };

pcie_core_pcie_a10_hip_0_altera_pcie_a10_hip_181_7tjtnma

instantiates altpcieav_256_app, which instantiates altpcieav_dma_hprxm, which instantiates altpcieav_dma_hprxm_rdwr. The error is in the assignment statement:

assign HPRxmAddress_o = { {(HPRXM_BAR_TYPE-BAR2_SIZE_MASK ){1'b0}}, rxm_address_reg[BAR2_SIZE_MASK -1:0] };

 

Apparently the index for rxm_address_reg is -1, which is due to setting BAR2_SIZE_MASK to 0 at the top of the hierarchy.

 

I do not see this problem if I build the PCIe core from the IP catalog, but we are having sim problems with that approach.

 

Is this a known bug?

 

Thanks.

 

 

 

 

 

 

 

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6 Replies
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Hi Daniel,

 

In order to better assist you, it will be great that if you can share the PCIe AVMM IP setting, and also what simulator that you are using?

 

From my side, I have performed the following test but did not see the problem in simulation:

 

  1. Generate the PCIe Gen3x4 AVMM example design from Platform designer by using Quartus v18.1
  2. Open Modelsim SE-64 10.6d
  3. Change the directory to /pcie_example_design_tb/pcie_example_design_tb/sim/mentor
  4. Type ld_debug from the transcript
  5. Add waveform
  6. Type run -all from the transcript
  7. The simulation is a success : - SUCCESS: Simulation stopped due to successful completion!

 

Regards -SK

 

 

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Beginner
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This post is not about a simulation problem - this is about a compile error when elaborating the design in Quartus.

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Hi,

 

Thank you for your reply. I did compile the example design that generates from the GUI, but unable to see the same error. I'm not aware of the error that you reported here. If possible, could you please attach the QAR file that can duplicate the problem, so that I can look into it further? Or you may use the example design as the starting point and see if you can still observe the same problem.

 

Regards -SK

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Hi,

 

Please do let me know if more help is needed. It will be helpful for us to understand the error if a problematic QAR file can be attached here. Thanks.

 

Regards -SK

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Beginner
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I have solved this problem. I built a PCIe endpoint with Avalon memory-mapped interface as .ip, rather than as a .qsys. Quartus allows this (and it seems to be fine for cores with the Avalon streaming interface), but it does not provide a way to program the BARs, i.e. to set the size of each addressable memory region. As a result, the BAR2_SIZE_MASK parameter is set to 0, and the upper index of rxm_address_reg[BAR2_SIZE_MASK -1:0] is a negative number (- 1). This causes the compile error.

 

The solution is to build a .qsys macro which contains just the PCIe core, and export the Avalon-MM master interfaces through bridges.

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Thank you for the update. This is glad to see the problem resolved.

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