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Altera_Forum
Honored Contributor I
683 Views

ddr controller ip performance

Hi, 

I am trying high performance ddr controller in my design. But I meet some performance problem when simulating it. First, the local_init_done signal goes high very late at about 4000us, but I have selected quick carlibration when generating the ip. Second, the RAS to CAS delay is too long about 12 ddr clock cycles, while I set the tRCD to 15ns in customed memory model. Then how can I solve these problems?:confused: 

 

Thanks! 

BTW, I use quartus II 9.0
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Altera_Forum
Honored Contributor I
34 Views

If I use quartus 10.0, the carlibration time can be minimized, but the RC delay is still very large for performance.

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