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Altera_Forum
Honored Contributor I
769 Views

CPRI IP - cpri_clkout problem

Hi there, 

 

I am new to Altera forums, so if you can please bare with me that will be great. 

 

I am currently working on a CPRI IP and trying to analyse the cpri_clkout signal from the IP after resetting it through NIOS. I am using Quartus II vers11.1 SP1  

 

I have attached the Signal tap file with this thread. For some reason the cpri_clkout signal seems to go haywire after the reset structure is implemented. Can you please help why this might be happening?
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2 Replies
Altera_Forum
Honored Contributor I
56 Views

what clock frequency are you using to sample the signals in signal tap? If the sample frequency is close to your cpri_clkout then the reading in signaltap doesn't mean anything. Either use a higher frequency clock or use a real scope on the FPGA pin.

Altera_Forum
Honored Contributor I
56 Views

Thanks Daixiwen, problem solved.  

 

I just had to tie down gxb_powerdown signal, by doing so the cpri_clkout dint reset itself.
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