FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6670 Discussions

design partion error:must drive an unregistered pin

Altera_Forum
Honored Contributor II
1,261 Views

I devide my design to 4 part, and had each part been full compiled successful, then i import the sub-design to the top design, but encounted an error: outclk port of clock control block"......." with CLOCK_TYPE parameter set to EXTERNAL_CLOCK_OUTPUT drives .........,but must drive an unregistered pin. 

 

i don't know what is that mean, who can help me with that error? thanks.
0 Kudos
2 Replies
Altera_Forum
Honored Contributor II
589 Views

Hello, 

Could you post a bit more info on your design. 

i.e. What is the "outclk port of clock control block"? and how is it driven within that module? 

What does it drive in your top level design? 

 

Could you post the exact wording of the Quartus error message too?
0 Kudos
Altera_Forum
Honored Contributor II
589 Views

Sounds like you have a clock or PLL in one of your sub designs. 

 

Try moving it up to the top of the entire design?
0 Kudos
Reply