dma read master and write master specification

[AWu6]

is there any document about the detail of sgdma read master and write master?

i can only get the simple doc with only signal spec, not timing diagram and spec, so I'm confused about how to use it separately without dispatcher.

[RichardTanSY_Intel]

DMA Read and Write Block:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_embedded_ip.pdf#page=378

Avalon Interface Specification (Typical Read and Write Transfers):

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_avalon_spec.pdf#page=21

In the Platform Designer, you can click on the Data_Write_Master and the it will shows an example of a waveform.

Click the details on the top right corner to learn more.