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eSPI Agent Core, writing response packet to PCTXFIFO

WFitt
Novice
276 Views

Hi,

The Intel eSPI Agent Core is receiving a PC_MEMWR32 (1 byte) packet from the eSPI master, an Intel Elkhart Lake CPU. I am reading out the PCRXFIFO via IP core's Avalon MM bus until RX queue is empty. I am getting the address and like to respond the associated data. So I am writing the following data in the PCTXFIFO (Ch) :

- Byte 1: 0Fh (cycle type)
- Byte 2: 00h (length MSB)
- Byte 3: 01h (length LSB)
- Byte 4: 55h (Data)

After that I am writing 01h (PCTXFIFO_AVAIL) to the IP core's Control Register (4h).

But the Agent is only sending DEFER, it doesn't send the response with the data.

 

What am I doing wrong in the processing above?

 

Regards

Wolfram

 

 

 

 

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11 Replies
Kenny_Tan
Moderator
256 Views

Hi,


Not sure if this is related to FPGA question?


Thanks,

Best regards,

Kenny Tan


WFitt
Novice
245 Views

Hi,

My question is relating to Intel eSPI Agent IP core used in Intel FPGA.

The PCTXFIFO und PCRXFIFO are parts of this IP Core.

In the IP Core's User's Manual on page 81 there is a short explanation how to use the FIFOs:

--------------------------------------------------------------------------------
"You must use the following format while sending the response packet to PCTXFIFO:

cycletype (SUCCESSFUL_COMPLETION_WITH_DATA/UNSUCCESSFUL_COMPLETION)
-> MSB length -> LSB length -> DATA (optional)
After writing a response packet to PCTXFIFO, you must write 1 to Avalon Control
Register (0x4h), indicating that the PCTXFIFO has a complete payload available.
Once this flag is triggered, the eSPI host is acknowledged (thru espi status
information) and fetchs the packet accordingly using the GET_PC command. Each
FIFO can only store one packet."
---------------------------------------------------------------------------------

I am not shure if I am understanding right and  I am sending the right data to the PCTXFIFO (see my initially question).

 

Regards

Wolfram

hareesh
Employee
203 Views

Hi,

may i know which document are you following because i didn't find related to this "You must use the following format while sending the response packet to PCTXFIFO in that page. if you don't mind please share that document link.


Thank you,


WFitt
Novice
194 Views

Hi,

Here is the link to the document: 7.6. Peripheral Channel Avalon Interface Use Model (intel.com)

 

Kind Regards

Wolfram

 

 

hareesh
Employee
149 Views

Hi,

actually i received different cases related to eSPI with same name. all case from you?


WFitt
Novice
138 Views

Hi,

Yes, I posted my questions relating to eSPI to this forum and to the Intel Premium Support.

 

Regards

Wolfram

hareesh
Employee
97 Views

Hi,



https://www.intel.com/content/dam/support/us/en/documents/software/chipset-software/327432-004_espi_...



this one is following intel espi spec basically


you can refer to above link 5.1 Cycle Types and Packet Format for more information



Thanks,


WFitt
Novice
90 Views

Thank you, In the meantime I have solved this problem.

 

This would have been the answer that I needed:

In the PCTXFIFO must be written (example):

- Byte 1: 0Fh (cycle type)
- Byte 2: 00h (length MSB)
- Byte 3: 01h (length LSB)
- Byte 4: 55h (Data)

Exactly this bytes I wrote in the FIFO.

I would have enjoyed your confirmation that I was right. 

 

My problem was caused by my VHDL code reading the PCRXFIFO.

Now it works fine.

 

Regards 

Wolfram

 

 

 

 

 

 

 

 

hareesh
Employee
85 Views

thanks for update. if you feel your problem is solved i will close this case. please conform


WFitt
Novice
75 Views

You can close the case.

 

Regards

Wolfram

 

hareesh
Employee
60 Views

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