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Hi,
I want to use Intel eSPI agent core in MAX10 device for accessing general addresses. Can I use peripheral channel with memory read(32-bit) and memory write(32-bit) for accessing the user defined addresses (or) Is it meant only for accessing the "PORT IO addresses " like port80 ?
Could anyone confirm on this
Regards
Theja
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Hi,
As I understand from the eSPI Specification, any level of peripheral can be accessed by the eSPI Master provided correct chip select decoding happens.
Please go through the spec in detail, especially section 3.2 Architecture Descriptions.
Regards
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Hi,
Do you have any further queries on this topic?
Regards
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Hi,
Thanks for your reply. Actually want to use this espi agent core slave for register read/write access i.e., CPU(host) will access this user defined registers through eSPI. Whether this is possible ?.
It will be great help if you share the example design or test bench or any simulation setup ..
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Hi,
The Intel eSPI Agent Core is receiving a PUT_MEMRD32_SHORT (1 byte) packet from the eSPI master. I am reading out the Non-posted RX FIFO('h10) via IP core's Avalon MM bus until RX queue is empty. I am getting the address and like to respond the associated data. So I am writing the following data in the NPTXFIFO (14h) :
- Byte 1: 0Fh (cycle type)
- Byte 2: 00h (length MSB)
- Byte 3: 00h (length LSB)
- Byte 4: 55h (Data)
After that I am writing 02h (NPTXFIFO_AVAIL) to the IP core's Control Register (4h).
But the Agent is only sending DEFER, it doesn't send the response with the data.
Is I am doing in correct way?
Regards
Theja
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Hi,
Are you generating the espi_cs_n while giving the commands to the eSPI agent core? It is difficult to tell the exact issue. Request you to send your design so that it can be simulated and checked for issues.
Regards
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As there is no response to this case, I am setting it to closure. Please feel free to open a new case.
Regards
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