ethernet_100g_loopback_off

[Vamsi_21]

Hi,

I have generated a low latency 100g design example by following the guide below:
https://www.intel.com/content/www/us/en/docs/programmable/683371/16-1/quick-start-guide.html

I tested the serial loopback on the development board, I was able to see the Rx and Tx stats.
But when i wanted to disable the loopback , i made the loop_off in the .tcl scripts and tested on the development board but it was still showing Rx and Tx stats.

Name of the board: ARRIA10 GX development board
Device: 10AX115S2F45I1SG

Below,  I am sharing the .qar of the design and the system console window output when the loop_off is done in the tcl scripts.

[Yi]

Hi,

TCL run_test file should automatically enable the loopback mode for testing, it should also be logged as well, you may see this in ethernet_100g_loop_off.jpg screenshot.

[Vamsi_21]

Hi,
I have made loop_off in the main.tcl script to check without loopback but still it is showing the tx statistics.
Below I am attaching the screenshots of the system console window.

[Yi]

It seems working as the Rx clk and recover clk are both 0Hz, and lock status = 0, though the MAC status looks weird to me either, would suggest to try some debug and see if the loop_off is correctly set or not first.

the process is in the *\hwtest\altera\alt_aeu_40\eth_ultra_phy_inc.tcl :

proc setphy_lpoff {} {

    global BASE_RXPHY

    global ADDR_PHY_PMALOOP

    # puts "RX PHY Register Access: Setting Serial PMA Loopback\n"

    reg_write  $BASE_RXPHY $ADDR_PHY_PMALOOP 0x0

    reg_read   $BASE_RXPHY $ADDR_PHY_PMALOOP

}

May edit the puts here to see if it's set or not first.

[Vamsi_21]

Hi,
I have kept some puts statements in the tcl scripts as you have suggested but for both loopback on and loopback off the rx clk=0 Hz, recover clk=0 Hz, lock status =0 and still it is showing both rx and tx mac stats. 

Iam sharing the tcl scripts and also I am attaching the screenshot of the system console window for both loopback on and loopback off.

[Yi]

Weird, Rx clock it not on even when loop is on? Are you able to use toolkit to check the Rx CDR when loopback is on?

[Vamsi_21]

Hi,
I have taken a signal tap file and added recover clk, reconfig clk to it.

I set the clock as clk_ref = 644.53125 MHZ
It was showing recover clk=0 and reconfig clk was running fine.
Below iam attaching a screenshot of the signal tap window.

[Vamsi_21]

Hi,
The transceiver toolkit is not launching after loading the design to check Rx CDR when loopback is on.

[Vamsi_21]

Hi ,
Is there any update?

@Yi 

[Yi]

Sorry for the late reply, I'm booking an A10 kit see if can replicate this issue on board, would let you know if any progress.

[Yi]

I tried on dev kit and it was able to get loop_on/off correctly, let me check your design to debug further.

[Yi]

I might find why you failed in board test, after open the .qar file, I found that the design you are using is the compilation test design, under folder:

/eth_100g_a10_22_2_0_94_restored/compilation_test_design

The compilation design is only for compilation test, which is not set for the board test.

To try on board, you can use the design file in folder /hardware_test_design , this should be the ready design that works for target dev kit.

Let me know if this works for you, thanks.

[Vamsi_21]

Hi,
I have tried to test on the dev kit with the design file in the /hardware_test_design but I am getting master_write _32error in the system console window.
Below I am attaching the screenshot the error.

[Chris039]

master_write _32error could be caused by the problem in the code or the clock. 

1. Is the example design without modification working?

2. If example design without modification is working, do modify anything on the design itself (RTL, pin assignment, etc) besides the TCL.

3. If no modification made besides the TCL, you have to review the TCL again and see which line causes the error

[Chris039]

Hi,

Any update from your side?

[Vamsi_21]

Hi,
I have tried with different pins assignments mainly FMC pins for tx and rx transceivers.

I am getting the below error:
"TTK failed reading from PHY slave, cannot enable TTK functionality for this PHY. Please verify the reconfig_clk is running and ensure this PHY is not stuck in reset."

[Chris039]

You can probably try running some example design and compare the pin assignment between the working version and the one you are seeing this error.

[Vamsi_21]

Hi,
The compilation _test_design is the only working version for which i got same results for both loop_on and loop_off as i mentioned earlier.
For the hardware_test_design there is no working version , I had always got the error:

"TTK failed reading from PHY slave, cannot enable TTK functionality for this PHY. Please verify the reconfig_clk is running and ensure this PHY is not stuck in reset." 

[Chris039]

I cannot find the hardware_test_design in the QAR that you have shared earlier. I tried to generate an example design using the ex_100g.ip. I notice that the pin assignment for the compilation_test_design in your QAR is different from the one generated. 

Can you share your latest compilation_test_design and hardware_test_design for comparison? Are you using this devkit?

https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/arria/10-gx.html

I believe you have to use the hardware_test_design for the hardware test but somehow the pin setting or clock input has problem. 

[Yi]

"TTK failed reading from PHY slave, cannot enable TTK functionality for this PHY. Please verify the reconfig_clk is running and ensure this PHY is not stuck in reset." 

In most cases, this failure is due to the wrong setting on the reconfig_clk to PHY, which may be the different input pin in .qsf

In the compilation design you shared, the reconfig_clk was auto assigned to pin AU15, which should be an clock input of the dev kit.

For your design, you'd assign this pin to a 100MHz clock input (if you are not using dev kit), or AR36/AR37 which should be the 100M sysclk input on the dev kit.

Also there's chance that clock is correct but reset was pulled, so PHY stuck in the reset mode, this you may also check the reset source or use ISSP to control the reset signal for a try.

[KhaiChein_Y_Intel]

Hi,

We do not receive any response from you to the previous question. This thread will be transitioned to community support. 

If you have a new question, feel free to open a new thread to get the support from Intel experts. 

Otherwise, the community users will continue to help you on this thread. 

Thank you.

Best regards,

Khai