false_path issue seen in the STA tool when running 'check_timing'

[Knug]

I set false path to the following signal :

set_false_path -from [get_ports fpga_nstatus]

& when I run STA check_timing reported 'no input delay was set on the input port'

Same with other false paths I set.

I am currently ignoring this. Please comment here.

On the other hand when I select 'Report Unconstrained paths' there were no unconstrained paths reported (as expected).

Why 'check_timing' reported that message ?

[RichardTanSY_Intel]

Hi @Knug 

Sorry for the late response. 

In Check Timing, the no_input_delay check verifies that every input port that is not determined to be a clock has an input delay assignment. Thus the message reported. 

Reference: https://www.intel.com/content/www/us/en/programmable/quartushelp/current/index.htm#analyze/sta/sta_com_check_timing.htm

You might have wrote a wrong sdc command thus no unconstrained paths reported. 

In the Timing Analyzer, you can set false path by clicking Constraints > Set False Path to ensure that the tool recognize the paths. 

You may checkout the user guide here on set_false_path sdc command and its example.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qpp-scripting.pdf

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos. 

[RichardTanSY_Intel]

I have yet to receive any response from you to the previous question/reply/answer that I have provided but I believed that I have answered your question. 
With that, I will now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.