Dear Intel Community,
I'm working with the FFT IP core provided by the Intel in Quartus. I've designed in vhdl a block that provides the input signal to the FFT IP core. The compilation in quartus in okay but when I try to perform the simulation in modelsim it returns the error vsim-3473 component instance fft_ii_0 is not bound.
Have I missed to insert some declarations in my simulation? How can I fix this error?
Thanks in advance
Can you help me by providing more information about Quartus tool edition & version, device,language used while generating this project ?
I think, this may be Warning & it may occur due to mismatch of instance declaration so I request you, recheck the "fft_ii_0" component instance ports & their width.
Let me know if this has helped resolve the issue you are facing or if you need any further assistance.
(This message was posted on behalf of Intel Corporation)
thank you for your answer. I'm using the Quartus Prime Edition v18.1 with Modelsim Free Edition and I'm writing VHDL code for the Ciclone IV. I've correctly generated the VHDL code associate with the FFT IP in my project and then I've added the file .sip and .qip. The quartus compilation ik okay but the simulation doesn't work. The code below represents the example of declaration generated by the IP that I've pasted in the code of my entity.
Please, any further suggests?
component fft_core is port ( clk : in std_logic := 'X'; -- clk reset_n : in std_logic := 'X'; -- reset_n sink_valid : in std_logic := 'X'; -- sink_valid sink_ready : out std_logic; -- sink_ready sink_error : in std_logic_vector(1 downto 0) := (others => 'X'); -- sink_error sink_sop : in std_logic := 'X'; -- sink_sop sink_eop : in std_logic := 'X'; -- sink_eop sink_real : in std_logic_vector(11 downto 0) := (others => 'X'); -- sink_real sink_imag : in std_logic_vector(11 downto 0) := (others => 'X'); -- sink_imag fftpts_in : in std_logic_vector(10 downto 0) := (others => 'X'); -- fftpts_in inverse : in std_logic_vector(0 downto 0) := (others => 'X'); -- inverse source_valid : out std_logic; -- source_valid source_ready : in std_logic := 'X'; -- source_ready source_error : out std_logic_vector(1 downto 0); -- source_error source_sop : out std_logic; -- source_sop source_eop : out std_logic; -- source_eop source_real : out std_logic_vector(11 downto 0); -- source_real source_imag : out std_logic_vector(11 downto 0); -- source_imag fftpts_out : out std_logic_vector(10 downto 0) -- fftpts_out ); end component fft_core;
Thank you in advance
I've resolved the problem. In VHDL code generation, the Megacore Wizard provides two files: fft_core.vhd and fft_core_ii_0.sv. This files have the same ports but different inizialization values (in the latter the input ports are inizialized to 'X' while in the former the ports are inizialized to '0'). In my entity I've changed the entity fft_core with fft_core_ii_0 and the warning disappears.
Now the FFT core seems to work but I've noted that the source_sop is always set to '1' while the source_eop is alway set to '0'. From the manual these to pin must indicate the start and the end of the frame. Is it a normal behaviour? Or there is a mistake?
Thank you in advance