FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6343 Discussions

fifo-less triple speed ethernet

Altera_Forum
Honored Contributor II
1,291 Views

Hello,  

Due to latency problem, I have to use Triple speed ethernet without internal fifos. Nevertheless, I have no piece of information about how to plug "receive_packet_type_0" or "receive_fifo_status_0" avalon stream. 

Could you please help me finding sopc design or technical exemple of project which use fifoless tse ip? 

 

Thanks. 

 

ps : i think that receive_packet_type_0 should be similar to valid data signal and receive_fifo_status_0 similar to almost full fifo signal but i didn't find anything about that.
0 Kudos
5 Replies
Altera_Forum
Honored Contributor II
279 Views

Hello again... 

I did some tests and i get this results : 

 

- receive stream : - 8 bits data signal 

- 1 bit ready signal 

- 1 bit valid signal 

- 5 bits error signal 

- 1 bit sop 

- 1 bit eop 

[/INDENT][/INDENT]- transmit stream : - 8 bits data signal 

- 1 bit ready signal 

- 1 bit valid signal 

- 1 bit error signal 

- 1 bit sop 

- 1 bit eop 

[/INDENT][/INDENT]- receive_packet_type : - 1 bit valid signal 

- 5 bit data signal 

[/INDENT][/INDENT]- receive_fifo_status : - 2 bits data signal 

- 1 bit valid signal 

[/INDENT][/INDENT]but i still don't know what's in the two last streams receive_fifo_status and receive_packet_type... and i still don't have any piece of information... 

 

Could anyone help? 

 

Thanks.
0 Kudos
Altera_Forum
Honored Contributor II
279 Views

Those signals are described in the "10/100/1000 Multi-Port Ethernet MAC Signals" chapter of the datasheet (page 4-81)

0 Kudos
Altera_Forum
Honored Contributor II
279 Views

I'm in the same boat.. 

 

Yes they are lightly documented in the user guide, but what does one "do" with those extra ports? In a single port design, I can click on "use internal fifos" and those ports vanish (presumably inside the black box), but I have to disable internal fifos to enable selecting up to 4 ports. 

 

In my case I want to verify a quad SGMII pinout in a Stratix IV before committing it to a PCB design. I don't care what kind of packet type comes in. 

 

For the fifo status bits, I don't know what to feed them. I have 8 individual fifos with no status pins showing. I terminated the ethernet data paths thru a format converter - fifo - dma engine - internal ram. I could add a fifo flag, but what type, and how do I map 8 fifos worth of flags into a single port in SOPC builder?
0 Kudos
Altera_Forum
Honored Contributor II
279 Views

if you don't care about the packet types, just ignore them. 

For the fifo status, you can just report that they aren't full. Just note that in that case the MAC can't use flow control, and you may loose packets or data if your fifos are full when a new packet arrives.
0 Kudos
Altera_Forum
Honored Contributor II
279 Views

Is there a solution available for connecting receive_packet_type_0 and receive_fifo_status_0? 

 

The receive_packet_type is a bit 5 data vector with a 1 bit valid, but the Avalon streaming interface requires multiples of 8 bits.
0 Kudos
Reply