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PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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frame reader configuration and initialization

Honored Contributor II

I use the frame reader in my design with the following settings: 

Bits per pixel per color plane: 8 

Number of color planes in parallel: 3 

Number of color planes in sequence: 1 

Maximum Image width: 1920 

Maximum Image height: 1080 

Master port width: 64 

Read master FIFO depth: 1024 

Read master FIFO burst target: 64 

Use separate clock for the Avalon MM master interface: unchecked  

Kindly confirm if the following calculations for number the words and the Single Cycle Color Patterns are true or not 

1- // Words 

IOWR(FRAMEREADER_BASE, 5, 259200); // (1920*1080*8*3)/48= 1036800 


2- // Single Cycle Color Patterns 

IOWR(FRAMEREADER_BASE, 6, 2073600); // 1920*1080=2073600 number of pixels in the frame multiplied by the number of single cycles required to represent one pixel 


Your reply will be highly appreciated
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