What is not working on your board? Design or testbench??
When you write a Verilog or VHDL code, you are writing code that will be translated into gates, registers, RAMs, etc. The program that performs this task is known as a Synthesis Tool.
It is the job of the Synthesis Tool to take your Verilog or VHDL code and turn it into something that the FPGA can understand(synthesizable code).
However, there are some parts of Verilog and VHDL that the FPGA simply cannot implement. When you write code like this, it is called non-synthesizable code.
When you write a testbench for simulation, often using non-synthesizable code, which can't be implemented on FPGA.
Thank you !
I don't know how to add my testbench file on board , it's like i programed my fpga just with the mean code without a testbench... but in modelsim it's working