FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6534 Discussions

help：DDR2 problem

Altera_Forum
Honored Contributor II
‎06-29-2011 02:55 AM
933 Views

Hi, I met a strange problem about DDR2 controller. I use the DDR2 SDRAM Controller v9.1. Sometimes the local_rdata has a value a cycle early before the local_rdata_valid is high and the following values are not what I have written into the ddr2 when local_rdata_valid is high. How can I solve this problem? Thank you very much.

0 Kudos

Link Copied

0 Replies
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.