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Altera_Forum
Honored Contributor I
736 Views

help: Genlock Function of CVO

I start to evaluate the Genlock function of CVO, but it can not lock to the source. 

(It is based on the UDX2_1_LABS lab3 from Altera; and Arria II GX Devkit+ HSMC-SDI) 

In the SOPC, CVI(sdi_in_1) connected to terminator, Test Pattern Generator connected to CVO(sdi_out_1). 

Outside the SOPC, sof and locked_sof from the CVI connected to CVO. 

 

In the Nios software, the_sdi_out_1.set_genlock(true) to enable CVO genlock function, but when read the status of CVO, it always not genlocked (the_sdi_out_1.is_genlocked()).  

 

The format of sdi_in_1 is PAL, and TPG and CVO is also set to PAL. 

I check the sof from the CVI, it is a 25Hz pulse, it should be OK. 

I check the CVO (sdi_out_1) output by SDI monitor, and it is OK. 

 

Please help me! 

 

Thanks.
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Altera_Forum
Honored Contributor I
36 Views

Hi, 

 

After set the CVO output clock tracing the SDI_IN clock using the vcxo, then the CVO output can genlocked to SDI_IN. 

 

:rolleyes:
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