the steps of my signal processing is as follows:
Analog data ->ADC ->FIFO ->FFT
the ADC sample rate is 200Msps, I want to implement FFT in the cyclone ii
FPGA with the FFT IP core, I want the clock of the FPGA is 100MHz, so how can i process the 200Msps data in 100MHz of clock rate and what is the function of the FIFO,
is it should be implement inside the FPGA or with a FIFO chip? I'm very puzzled about it.
