:confused: Hi,I need help in compiling a stritixIII project with 2 identical ddr_hp_controller v.9 instantiation. In my design, a Megawizard generated ddr_hp_controller v.9 is instantiated twice in sub-blocks. I must give two prefixes for ddr memory interface pin names in my top-level file to differentiate each controller. But I only get one "ddr_controller_pin_assignment.tcl" file. I have tried to modify the default "variation_name_pin_assignment.tcl" file and generate two pin assignment tcl files with two different prefix settings and run these two tcl files before compile. But it is failed when compiling the project. What is the correct way to generate two different prefixes by editing the pin_assignment tcl file? Your inputs are most appreciated!
I believe the tcl file should be able to work out you have 2 interfaces and apply assignments for both, you dont need to edit it. Did you try just running it?What version of Quartus are you using?
Thank you for your response! :)I have two ddr interfaces. I have created two pin assignment tcl files by editing the original variation_pin_assingment.tcl. In each new pin assignment file, I replaced the original "mem" prefix with the new one, such as "a_mem" and "b_mem", respectively. Then, I ran the new "variation_a_pin_assignments.tcl" and "variation_b_pin_assignments.tcl" before I compile the project. But only variation_a 's pins got recognized and grouped. I could not find the clear statement in altera manual regarding assign multiple prefixes for instantiating one ddr_hp_controller multi times. I have tried this on Quartus v.9.0 sp1 and v.9.1 sp 2, and got same errors:confused:. liza_altera
Dont edit anything. The original tcl script is smart enough to work out you have two interfaces and it will set all the correct assignments for both.You may have to start again if you have altered this file.
Thanks again Std_logic!As you suggested, without any prefix editing, I have used the default variation_pin_assignment.tcl to compile my project, which instantiated a ddr_hp_controller twice with a_mem and b_mem interfaces. The compiling has been through without error message . But when I looked at that "variation_phy_autodetectedpins.tcl" , only the pins for a_mem port are listed. Why my b_mem port pins are not there? Is the b port really connected? I am confused. Your input is most appreciated. Thanks!
In the assignment editor do you have assignments for both interfaces? If so then it worked.From the compilation report you should be able to see if 2 controllers have been instantiated as well.
1 - Make two copies of the file.2 - Edit each TCL file to have the appropriate name prefix. 3 - Run one of the TCL files. 4 - Close Quartus 5 - Re-open Quartus and your project. 6 - Run the other TCL file. If that works, let me know and I'll explain the problem. Jake
Thank you Std_logic!I do see the two ddr controllers get instantiated in my compile report file. I just don't understand why that variation_autodetectpins.tcl does not show my b_mem pins.
Thank you Jakeobjones!:)I will try the experiment you suggested. Is it weird if one have to open-close the Quartus to do the trick? I will let you know the result.
Jake,I did what you suggested. Run two xxx_pinassignment.tcl files in separate times. The compilation was through but I still got only one set of ddr port name shown in that xxx_phy_autodetectedpins.tcl. It seems that no matter using default xxx_pinassignment.tcl without any user prefix assignment or using two separate pinassignment.tcl with user prefix assignments, the compilation results are same. :confused: Liza_altera