FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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how to solve this below mentioned error?

fArum
Beginner
300 Views

I am simulating PCIE IP (Arria V) in questa sim . I have compiled the altera libraries along with design and testbench files but while simulating I am getting this error recompile work.tb_top because sv_std.std has changed.

 

Note: Note : I have included the libraries while simulating. (vsim -L lpm_ver -L arriav_pcie_hip_ver -L altera_ver -L altera_lnsim_ver -L sgate_ver -L arriav_ver -L arriav_hssi_ver -L altera_mf_ver -novopt work.tb_top -l sim.log)

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2 Replies
BoonT_Intel
Moderator
140 Views

Hello, what error that you facing? seem like you are not include the error message.

Anyway, I will suggest you to try the example design simulation and compare it with your compilation. to run the example design simulation, generate the example design and run it with steps explain in this document: https://www.intel.cn/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-01105-1_6.pdf#page=27

fArum
Beginner
140 Views

herewith I have attached the error message, which I am facing on

simulation.

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