How can I make sure that the incoming data from memory is the response to memory read request and is also valid?
I am using Avalon Memory-Mapped Interface and I want to get a valid signal for each data that I request from memory by a readdata request.
Can I use this condition: (response == 0)? Does it arrive at the same clock that data arrives?
Note that I am using a fixed-latency read, so I am not able to use readdatavalid signal.
Since the issue addressed had been resolved.
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