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i want to use high performance controller ii ,but is puzzled by local_burstbegin??

Altera_Forum
Honored Contributor II
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https://www.alteraforum.com/forum/attachment.php?attachmentid=9308  

need help please  

i will use the high performance controller ii directly ,and will not use sopc 

i have noticed that the hpcii example uses the signal of local_burstbegin ,local_write_req and local_ready to implement burst write data to DDR2,and firstly there is local_burstbegin of one clk(i understand this burstbegin is to prepare for the really burst operation next), then wait for serial clk( is the number is fixed to wait for 6 clk ??,because i count in the wave ,and there are 6 clk , but i can not find speciation anywhere ) ,and again the local_burstbegin ,local_write_req is given (on the same time ,the local_ready signal is asserted),and on the same time the beginning address and data is given on the bus,and the burst write is complete 

 

my questions :1) how many clk should wait for between the prepare local_burstbegin and the next realy write local_burstbegin,i can not find speciation anywhere ,and i count the wave figure to get the wait number of clk ,that is 6 clk ,is it right ?? 

2) is this the standard operation mode for every burst write?? 

3) if i want to write 64 byte ,how can i use the burst mode?(such as the ddr2 data width is dq = 8bit,and burst length is 4 ) ? i need two burst to complete the 512byte write, can i give the firstly prepare local_burstbegin of one clk for only once, and then i can carry on the really burst operation to write 512 byres but need not to give the prepare burstbegin signal again in the process?
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