FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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in the ALTLVDS_ RX Only ip core i want to syncronize the start data as in the page attached how i do it

OADAM1
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SreekumarR_G_Intel
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Can you send me the design file you started with ? I will start from that and send back working file with Texas ADC Interface for one channel.

 

Thank you ,

 

Regards,

Sree

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