input for HDL import

[Altera_Forum]

Let say if i have InputAlteraBlockset with the bus type set as fractional integer [4].[4] and connect to the HDL import blockset, is that possible? What input format should the HDL import blockset has in order to be compatible with the fractional input? I have tried both std_logic_vector(7 downto 0) or sfixed(3 downto -4) and it I couldnt the expected result.  

 any suggestion/advice?? thanks alot!!!

[Altera_Forum]

(7 downto 0) should work... if not, you can try upscaling your [4].[4] input bus to [7].[0] before passing into your imported HDL... if it still doesn't work, then chances are, you need to recheck your HDL code.