hello everyone,'m quite newbie in Quartus 10.1.Rightnow i m working on a project in which i need to work on quartus 10.1 (sp1),so as u all might know that there is one new feature of Qsys in Quartus 10.1.And in qsys,there is no directly provision of tristate bridge to which sdram and flash -data and address lines are shared.Instead there are 3 stages for creating tristate bridge (generic trisate controller,pin sharer,tristate bridge) I have read "qsys interconnect" and design examples also provided by that.in which they have given some notes on this,but i don't know how to interface them,i have tried but not able to understanding means how to set the parameters for both of them in generic tristate con.??:( So anyone please post sample and very small Qsys system or just a screen shot containing "clock source,nios II,jtag uart,timer,sdram,flash,pll"???? Any idea or suggestion would b greatly appreciated.:)
You can do one of these:Bring in an old SOPC Builder design, Qsys should take all the Tristate components and replace them with the new components. Here is the connectivity you would use to wire up the new tristate scheme:
Generic Tri-state controller (SSRAM) --> Tristate pin sharer --> Tristate bridge Generic Tri-state controller (Flash) -->The generic tri-state controllers have a regular Avalon slave interface which you then connect to the masters in your system. If you are still stuck send me a PM with your email address and I will look for a design I can forward your way containing a flash and ssram. The new tri-state scheme uses "tri-state conduit" masters and slaves to do the connectivity so in my nasty ASCII art drawing the master connections are on the left and slaves on the write of each connection point.