I have some doubt about DDR memory controller:
I found the ddr controller doesn't support 64M bytes(32M X16) single ddr memory chip, can I modify the address lines of this IP?
I add a ddr controller,but why my SOPC doesn't require a PLL for memory controller?
by the way
quartus warning:
1.
Info: Pin write_clk_to_the_ddr_sdram not assigned to an exact location on the device,
But I can't find this signal on memory chip.
2.
Warning: Setup slack is -6 ps associated with pin 'ddr_dq_to_and_from_the_ddr_sdram[4]' ( variation port 'dq(4)', 'input_cell_L[0]') ( Total of 2 paths with negative slack)
thanks for helping me.
