FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6359 Discussions

is it a bug in the SDI interface ip?

Altera_Forum
Honored Contributor II
962 Views

i use the SDI-INTERFACE IP to generate the HD-SDI signal. i first test the 1080i60 signal. use the SDI monitor to test the signal, i found the line number only encodered into the Cb/Cr's position , the y's position is not encodered the line number , always 10'h200.  

 

 

the monitor 's data is as following: 

 

SAMPLE Y Cb/Cr 

[EAV] <1920> 3FF 3FF 

[EAV] <1921> 000 000 

[EAV] <1922> 000 000 

[EAV] <1923> 2D8 2D8 

<1924> 200 204 

<1925> 200 200 

 

the line number has not been encodered into the corresponding position. 

 

according to the SMPTE292M 5-2 the line 1924's Y postion should also be 204. 

 

the following is the corresponding code of the SDI signal generator.  

The sdi_if module is the SDI INTERFACE interface.  

The test_vips module is the video pattern generator ip. I use the signal-tap test the line number(tx_ln) it output is write. 

 

wire [10:0] tx_ln;  

 

test_vips DUT 

...... 

.vid_ln_from_the_alt_vip_itc_0 (tx_ln), 

//line number output,11 bits. 

...... 

); 

sdi_if SDI_IF( 

...... 

.tx_ln({11'b0,tx_ln}), 

..... 

);
0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
189 Views

today i changed the code,modified the SDI_IF as following: 

 

sdi_if SDI_IF( 

...... 

.tx_ln({tx_ln,tx_ln}), 

..... 

); 

 

then the problem was solved, the line number inserted into the right position. 

 

but the SDI MegaCore Function User Guide v9.0 page 3-27 said tx_ln signal when HD-SDI: bits 21:11 11'd0;bits10:0 LN. I suggest Altera should change this line to HD-SDI: bits 21:11 LN;bits10:0 LN. 

 

other defination i am testing .......
0 Kudos
Reply